The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
A memory device includes a memory device controller and non-volatile memory (such as in the form of one or more memory integrated circuit chips) in communication with the memory device controller. The non-volatile memory may be composed of memory cells that can be programmed to store a single bit or a single level, being termed a single-level cell (SLC), whereas other memory cells in the non-volatile memory may be programmed to store multiple bits or multiple levels, being termed multi-level cells (MLC).
In one operation, data stored in an SLC block may be folded into an MLC block. In this regard, data may be folded into a target MLC block of the solid state memory, such as when data is moved from one or more source SLC blocks to the target MLC block. In the folding process, errors may occur whereby the data stored in the target MLC block contains differences in the values as compared to the values stored in the source SLC blocks. To identify errors, an enhanced post-write read (EPWR) may be performed whereby the values stored in the target MLC block may be read and compared with the values stored in the source SLC blocks to identify the errors.